BSCS Computer Architecture and Organization 2 — Questions and Answers
Question 1: What is the function of the memory address register (MAR)?
- Stores data read from memory
- Holds the address of memory to be read or written (Correct answer)
- Counts memory accesses
- Manages virtual memory mapping
Correct answer: Holds the address of memory to be read or written
The MAR holds the address of the memory location currently being accessed during a read or write operation.
Question 2: Which bus carries data between the CPU, memory, and I/O devices?
- Address bus
- Control bus
- Data bus (Correct answer)
- System bus
Correct answer: Data bus
The data bus transfers the actual data between components; its width (8, 16, 32, 64 bits) determines how much data moves per transfer.
Question 3: What is RISC in computer architecture?
- Reduced Instruction Set Computer (Correct answer)
- Rapid Integrated System Computing
- Remote Instruction Set Control
- Refined Integrated Scalar Computer
Correct answer: Reduced Instruction Set Computer
RISC architectures use a small, highly optimized set of instructions that execute in a single clock cycle.
Question 4: Which technique allows a CPU to begin executing instructions before a branch condition is resolved?
- Out-of-order execution
- Branch prediction
- Speculative execution (Correct answer)
- Superscalar execution
Correct answer: Speculative execution
Speculative execution allows the CPU to execute instructions along a predicted path before knowing if that path is correct.
Question 5: What does DMA stand for and what does it do?
- Dynamic Memory Allocation — allocates RAM dynamically
- Direct Memory Access — transfers data without CPU involvement (Correct answer)
- Data Management Architecture — organizes storage
- Distributed Memory Array — connects RAM modules
Correct answer: Direct Memory Access — transfers data without CPU involvement
DMA (Direct Memory Access) allows peripherals to read/write memory directly, freeing the CPU for other tasks.
Question 6: What is the von Neumann bottleneck?
- The CPU cannot perform floating-point operations fast enough
- The shared bus between CPU and memory limits throughput (Correct answer)
- Cache misses slow down instruction execution
- Multiple cores compete for the same ALU
Correct answer: The shared bus between CPU and memory limits throughput
The von Neumann bottleneck is the limited data transfer rate between CPU and memory due to a shared bus for instructions and data.
BSCS Computer Architecture and Organization 2
What is the function of the memory address register (MAR)?