BEE Digital Logic and Design 3 — Questions and Answers
Question 1: Which Boolean identity is known as De Morgan's first theorem?
- A + B = A · B
- (A · B)' = A' + B' (Correct answer)
- A + A' = 1
- A · (B + C) = A·B + A·C
Correct answer: (A · B)' = A' + B'
De Morgan's first theorem states that the complement of a product equals the sum of complements: (A·B)' = A' + B'.
Question 2: In a JK flip-flop, which input combination causes the output to toggle?
- J=0, K=0
- J=1, K=0
- J=0, K=1
- J=1, K=1 (Correct answer)
Correct answer: J=1, K=1
When both J=1 and K=1, the JK flip-flop toggles its output on each active clock edge, resolving the indeterminate state of the SR flip-flop.
Question 3: A 4-bit magnitude comparator compares two 4-bit numbers A and B. How many output pins does it typically have?
- 1
- 2
- 3 (Correct answer)
- 4
Correct answer: 3
A standard 4-bit magnitude comparator (e.g., 74HC85) has three outputs: A>B, A=B, and A<B.
Question 4: What does the term 'propagation delay' refer to in a logic gate?
- The time for a signal to travel across the PCB trace
- The time between an input change and the resulting output change (Correct answer)
- The setup time of a flip-flop
- The fan-out loading effect
Correct answer: The time between an input change and the resulting output change
Propagation delay (tpd) is the time interval between a specified input transition and the corresponding output transition of a logic gate.
Question 5: Which type of ROM is electrically erasable and reprogrammable using byte-level erase operations?
- Mask ROM
- PROM
- EPROM
- EEPROM (Correct answer)
Correct answer: EEPROM
EEPROM (Electrically Erasable Programmable ROM) can be erased and reprogrammed electrically at the byte level without UV light.
Question 6: In a PLA (Programmable Logic Array), which two planes are programmable?
- Input and output planes
- AND plane and OR plane (Correct answer)
- Decoder and multiplexer planes
- Sum and carry planes
Correct answer: AND plane and OR plane
A PLA has both a programmable AND plane (for product terms) and a programmable OR plane (for sum of products), offering maximum flexibility.
Question 7: What is the minimum number of NAND gates required to implement a 2-input XNOR function?
- 3
- 4
- 5 (Correct answer)
- 6
Correct answer: 5
A 2-input XNOR using only NAND gates requires 5 NAND gates, first implementing XOR with 4 gates and then inverting with a 5th.
BEE Digital Logic and Design 3
Which Boolean identity is known as De Morgan's first theorem?