BEE Digital Circuits 3 — Questions and Answers
Question 1: What is the primary advantage of using Gray code in shaft encoders compared to standard binary code?
- Fewer bits are required
- Only one bit changes between consecutive values (Correct answer)
- It is self-correcting
- It supports floating-point representation
Correct answer: Only one bit changes between consecutive values
Gray code is designed so that consecutive values differ by exactly one bit, eliminating transition errors when multiple bits would otherwise change simultaneously.
Question 2: Which Boolean expression is correctly simplified using De Morgan's theorem: NOT(A AND B)?
- NOT(A) AND NOT(B)
- NOT(A) OR NOT(B) (Correct answer)
- A OR B
- NOT(A OR B)
Correct answer: NOT(A) OR NOT(B)
De Morgan's theorem states that NOT(A·B) = NOT(A) + NOT(B), converting NAND to OR of complements.
Question 3: A 4-to-1 multiplexer has select lines S1 and S0 with S1=1, S0=0. Which input is routed to the output?
- I0
- I1
- I2 (Correct answer)
- I3
Correct answer: I2
With S1=1 and S0=0, the binary select value is 10₂ = 2, so input I2 is selected.
Question 4: What is the output of a D flip-flop on the rising clock edge when D=0 and the current state Q=1?
- Q remains 1
- Q becomes 0 (Correct answer)
- Q toggles to 0 then 1
- Q is undefined
Correct answer: Q becomes 0
A D flip-flop samples D on the active clock edge and transfers it directly to Q, so Q becomes 0 regardless of the previous state.
Question 5: In a Karnaugh map for a 3-variable function, a group of four 1-cells eliminates how many variables?
- 1
- 2 (Correct answer)
- 3
- 0
Correct answer: 2
Each doubling of the group size (1→2→4→8) eliminates one additional variable, so a group of 4 eliminates 2 variables from the expression.
Question 6: Which sequential circuit type stores its current state in an array of flip-flops and uses combinational logic for next-state and output?
- Combinational PLA
- Finite state machine (Correct answer)
- Ripple adder
- ROM lookup table
Correct answer: Finite state machine
A finite state machine (FSM) consists of flip-flops holding the current state and combinational next-state/output logic driven by that state and inputs.
Question 7: The propagation delay of a gate is 5 ns. What is the maximum clock frequency for a pipeline stage containing 8 such gates in series?
- 200 MHz
- 160 MHz
- 25 MHz (Correct answer)
- 40 MHz
Correct answer: 25 MHz
Total delay = 8 × 5 ns = 40 ns; maximum frequency = 1/40 ns = 25 MHz.
BEE Digital Circuits 3
What is the primary advantage of using Gray code in shaft encoders compared to standard binary code?