Digital Logic and Design Flashcards

Which minimization technique uses a graphical map to simplify Boolean expressions by grouping adjacent 1s?

Answer: Karnaugh map

A Karnaugh map (K-map) is a graphical tool that simplifies Boolean expressions by visually grouping adjacent cells containing 1s into power-of-2 groups.

In a D flip-flop, what is the output Q after a rising clock edge if D = 0 and the current Q = 1?

Answer: Q becomes 0

A D flip-flop captures the value of D on the active clock edge, so Q takes the value of D (0) regardless of its previous state.

A full adder produces a Sum and a Carry-out. What is the Carry-out when A=1, B=1, Cin=1?

Answer: 1

With A=1, B=1, Cin=1, the total is 3 (binary 11), so Carry-out=1 and Sum=1.

Which of the following represents a hazard in combinational logic circuits?

Answer: A momentary glitch in the output during input transitions

A hazard is a momentary spurious output glitch caused by unequal propagation delays along different signal paths during input transitions.

What is the primary advantage of a synchronous counter over an asynchronous (ripple) counter?

Answer: All flip-flops are clocked simultaneously, eliminating cumulative delay

In a synchronous counter all flip-flops share the same clock, so state transitions occur simultaneously and cumulative ripple delay is eliminated.

Which logic family is characterized by the lowest static power dissipation at zero frequency?

Answer: CMOS

CMOS dissipates nearly zero static power because in steady state either the PMOS or NMOS transistor is off, blocking DC current flow.

A 3-to-8 line decoder with an active-low enable (EN') is used. If EN'=1, what is the state of all outputs?

Answer: All outputs are HIGH

With active-low enable asserted high (disabled), all decoder outputs remain in their inactive (HIGH) state since active-low outputs go HIGH when not selected.