B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Computer Architecture 4 — Questions and Answers
Question 1: Which storage class in the memory hierarchy typically offers the highest bandwidth but the smallest capacity?
- CPU registers (Correct answer)
- L1 cache
- DRAM
- SSD
Correct answer: CPU registers
CPU registers are on-chip storage directly accessible by the ALU in a single cycle, providing the highest throughput but limited to a few dozen slots.
Question 2: In IEEE 754 single-precision floating point, how many bits are allocated to the exponent field?
- 8 (Correct answer)
- 23
- 1
- 16
Correct answer: 8
IEEE 754 single-precision uses 1 sign bit, 8 exponent bits with a bias of 127, and 23 mantissa bits for a total of 32 bits.
Question 3: Which technique allows multiple processes to share a single physical memory region by mapping it into each process's virtual address space?
- Shared memory mapping (Correct answer)
- Copy-on-write paging
- Demand paging
- Segmentation faulting
Correct answer: Shared memory mapping
Shared memory mapping lets multiple processes map the same physical frames, enabling efficient inter-process communication without data copying.
Question 4: In a VLIW (Very Long Instruction Word) architecture, the responsibility for detecting and scheduling independent operations falls on:
- The compiler (Correct answer)
- The hardware scoreboard
- The OS scheduler
- The branch predictor
Correct answer: The compiler
VLIW relies on the compiler to statically pack multiple independent operations into a single wide instruction word, eliminating runtime hazard detection hardware.
Question 5: Which cache replacement policy will always produce the fewest misses if future access patterns are known?
- Optimal (Bélády's algorithm) (Correct answer)
- LRU
- FIFO
- Random
Correct answer: Optimal (Bélády's algorithm)
Bélády's algorithm evicts the block whose next use is furthest in the future, guaranteeing the minimum possible miss rate given perfect future knowledge.
Question 6: A processor uses non-uniform memory access (NUMA). A thread migrated to a remote NUMA node will experience:
- Higher latency when accessing its home node's memory (Correct answer)
- Lower latency for all memory accesses
- No change in memory latency
- Reduced cache miss rate
Correct answer: Higher latency when accessing its home node's memory
In NUMA systems, memory attached to a remote node is accessed over an interconnect, incurring higher latency and lower bandwidth than local node memory.
Question 7: Which execution model does a systolic array implement?
- Data flows rhythmically through a fixed network of processing elements (Correct answer)
- A single processor executes instructions sequentially
- Multiple threads share a single instruction stream
- Instructions are dispatched in dataflow order at runtime
Correct answer: Data flows rhythmically through a fixed network of processing elements
Systolic arrays pass data through a regular grid of simple PEs in a pipelined, lock-step fashion, efficiently implementing operations like matrix multiplication.
B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Computer Architecture 4
Which storage class in the memory hierarchy typically offers the highest bandwidth but the smallest capacity?