B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Computer Architecture 3 — Questions and Answers
Question 1: A direct-mapped cache with 16 KB capacity, 32-byte blocks, and 32-bit addresses uses how many index bits?
- 9 (Correct answer)
- 5
- 14
- 18
Correct answer: 9
16 KB / 32 bytes = 512 cache lines, requiring log2(512) = 9 index bits to select a line.
Question 2: Which branch prediction strategy uses a two-bit saturating counter to reduce mispredictions on loops?
- Two-bit predictor (Correct answer)
- Static always-taken
- One-bit predictor
- BTB-only prediction
Correct answer: Two-bit predictor
A two-bit saturating counter must mis-predict twice before changing state, making it more stable for loop branches than a one-bit scheme.
Question 3: SIMD (Single Instruction, Multiple Data) is best suited for which type of computation?
- Data-parallel operations on arrays of the same type (Correct answer)
- Recursive algorithms with deep call stacks
- Irregular graph traversal
- OS interrupt handling
Correct answer: Data-parallel operations on arrays of the same type
SIMD applies one operation simultaneously to multiple data elements packed into wide registers, ideal for vector, image, and signal processing workloads.
Question 4: In the MESI cache coherence protocol, a cache line transitions from Exclusive to Modified when:
- The local processor performs a write to it (Correct answer)
- Another processor reads it
- A cache flush occurs
- The block is evicted
Correct answer: The local processor performs a write to it
An Exclusive line is clean and privately owned; when the owning processor writes to it, it becomes Modified (dirty) without needing a bus transaction.
Question 5: Which interconnect topology provides the lowest latency between any two nodes in a small cluster?
- Fully connected (crossbar) (Correct answer)
- Ring
- Mesh
- Hypercube
Correct answer: Fully connected (crossbar)
A fully connected crossbar gives every node a direct link to every other node, resulting in a constant one-hop latency regardless of cluster size.
Question 6: Register renaming in out-of-order processors primarily eliminates which type of hazard?
- WAR and WAW (false) hazards (Correct answer)
- RAW (true) data hazards
- Control hazards
- Structural hazards
Correct answer: WAR and WAW (false) hazards
Register renaming maps architectural registers to physical registers, removing write-after-read and write-after-write name dependencies that are not true data dependencies.
Question 7: What does a reorder buffer (ROB) primarily enable in a superscalar processor?
- In-order commit of instructions after out-of-order execution (Correct answer)
- Parallel fetch of multiple instruction streams
- Translation of virtual to physical addresses
- Scheduling of memory bus transactions
Correct answer: In-order commit of instructions after out-of-order execution
The ROB holds instructions until they are ready to retire in program order, allowing precise exception handling despite out-of-order execution.
B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Computer Architecture 3
A direct-mapped cache with 16 KB capacity, 32-byte blocks, and 32-bit addresses uses how many index bits?