The Bachelor of Computer Engineering (BCompE) qualifying and entrance examinations test a rigorous combination of hardware-oriented fundamentals that distinguish the degree from both pure Computer Science and Electrical Engineering programmes. From Boolean algebra and sequential circuits to CPU pipeline design and embedded systems programming, these exams demand both conceptual depth and problem-solving speed. Our free PDF brings together practice questions across all major BCompE examination domains so you can identify your weak areas, drill the right material, and walk into your exam prepared.
Download the PDF and work through questions topic by topic or simulate timed exam conditions by attempting a full set in one sitting. Each answer includes a step-by-step explanation covering the underlying principle — not just the correct option — so you build transferable understanding rather than pattern-matching on answer choices.
Digital logic is the bedrock of every BCompE curriculum, and it consistently appears as the largest single topic area in qualifying examinations. Boolean algebra provides the mathematical language of logic: you must be fluent in applying De Morgan's laws, simplifying expressions using Boolean identities, and minimising logic functions using Karnaugh maps (K-maps) for up to four variables. K-map simplification errors — forgetting to group in powers of two, overlooking don't-care conditions, or missing the largest possible groupings — are among the most common sources of lost marks. Practice with both Sum of Products (SOP) and Product of Sums (POS) forms until the process is automatic.
Combinational circuits built from basic gates — AND, OR, NOT, NAND, NOR, XOR, XNOR — must be analysed and designed fluently. You should be able to construct truth tables from circuit diagrams and reverse the process: derive a minimal gate implementation from a truth table. Sequential circuits introduce memory via flip-flops: SR, D, JK, and T types each have characteristic equations and timing behaviours that exam questions probe through state table construction and timing diagram analysis. Finite State Machines (FSMs) — both Mealy and Moore types — appear frequently; given a word description of a sequential system, you must derive the state diagram, encode states, write excitation equations, and draw the resulting circuit. Our PDF includes worked FSM problems at exam difficulty level.
Computer architecture questions test your understanding of how hardware executes software efficiently. The classic five-stage RISC pipeline — Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), Write Back (WB) — is the standard model, and exam questions explore all three categories of pipeline hazard. Structural hazards occur when two instructions need the same hardware resource simultaneously (e.g., a single memory port for both instruction fetch and data access). Data hazards — RAW (read after write), WAW (write after write), and WAR (write after read) — arise from instruction dependencies; solutions include forwarding/bypassing, inserting NOPs, and compiler-based instruction reordering. Control hazards result from branch instructions that change the PC before the pipeline has resolved the target; branch prediction (static and dynamic), delayed branching, and branch target buffers are the standard mitigation strategies.
Memory hierarchy questions centre on cache organisation and performance. You must understand direct-mapped, set-associative, and fully associative cache structures: given an address, you should be able to determine the cache index, tag, and block offset fields and calculate whether a hit or miss occurs. Cache replacement policies (LRU, FIFO, random) and write policies (write-through vs. write-back with write-allocate) appear in both multiple-choice and calculation problems. Average Memory Access Time (AMAT) calculations — combining hit time, miss rate, and miss penalty recursively through L1/L2/L3 levels — are a quantitative staple. Bus architecture questions cover synchronous vs. asynchronous buses, arbitration schemes (daisy chain, centralised parallel, distributed), and bandwidth calculations. Our PDF includes multi-step problems that combine pipeline analysis with AMAT calculations, mirroring the integrative questions common on BCompE qualifying exams.
Embedded systems is a defining area of the BCompE degree and a topic area that pure Computer Science programmes cover only superficially. At the qualifying exam level, you are expected to understand microcontroller architecture — the interplay of CPU core, flash/EEPROM memory, RAM, GPIO ports, timers, ADC, UART/SPI/I2C communication peripherals, and interrupt controllers. Interrupt-driven programming questions typically present a scenario (e.g., a sensor that must be sampled within 100 microseconds of a trigger) and ask you to design or evaluate an interrupt service routine (ISR) structure. Key concepts include interrupt latency, ISR re-entrancy, volatile variable declaration in C to prevent compiler optimisation errors, and priority schemes in nested interrupt architectures.
Real-time constraints distinguish embedded systems from general-purpose computing. Rate-monotonic scheduling (RMS), the earliest-deadline-first (EDF) algorithm, and the utilisation bound test for schedulability are standard exam topics. For signals and systems, BCompE qualifying exams typically cover the Fourier series representation of periodic signals, the Discrete Fourier Transform (DFT) and its computational shortcut the FFT, the sampling theorem (Nyquist criterion: sample rate must be at least twice the highest signal frequency to avoid aliasing), and basic filter classifications (low-pass, high-pass, band-pass). These topics bridge electrical engineering and software signal processing and appear in BCompE exams at institutions that emphasise the hardware-software interface dimension of the degree.
Unlike Computer Science qualifying exams that emphasise algorithms and data structures, BCompE qualifying exams test programming knowledge with a hardware orientation. In C, you must be comfortable with pointer arithmetic — including pointer-to-pointer, function pointers, and the relationship between arrays and pointers — as well as memory layout (stack vs. heap vs. static memory), bitwise operations (masking, shifting, setting and clearing individual bits in hardware registers), and the use of volatile, const, and restrict qualifiers in embedded contexts. Struct packing, union types for memory-mapped register access, and fixed-width integer types from <stdint.h> are all fair game.
Assembly language questions test conceptual understanding rather than proficiency in a specific ISA. You should understand the role of general-purpose registers, the program counter (PC), the stack pointer (SP), the frame pointer (FP), and the status/flags register. Common question types include tracing through a short assembly sequence to determine the final register values, converting between C and assembly for simple loops or conditional branches, and explaining the calling convention for function calls (parameter passing, return value, caller-saved vs. callee-saved registers). Understanding how C constructs map to assembly is particularly important for embedded systems work where performance and memory footprint matter. Our PDF covers all of these areas with problems at both introductory and qualifying-exam difficulty, giving you a graduated preparation path regardless of your current starting point.
Solid exam preparation means covering every domain — not just the topics you already find comfortable. Download the free BCompE Practice Test PDF above and use it to map your current knowledge gaps across digital logic, architecture, embedded systems, and programming. For more practice with instant scoring and full explanations, explore our BCompE practice tests online quiz bank, updated regularly with new questions across all qualifying exam domains.