IT Computer Architecture 3

Question 1

What is the purpose of branch prediction in a CPU pipeline?

Accepted Answer

To speculatively execute instructions after a conditional branch to avoid pipeline stalls

Answer

To predict which cache level will contain needed data

Answer

To route operands to the correct ALU functional unit

Answer

To predict memory access patterns for prefetching data

Question 2

What does the Instruction Register (IR) hold during CPU operation?

Accepted Answer

The currently fetched instruction being decoded and executed

Answer

The address of the next instruction to execute

Answer

The result of the most recent ALU operation

Answer

The base address of the running program

Question 3

What does SIMD stand for in computer architecture?

Accepted Answer

Single Instruction Multiple Data

Answer

Sequential Instruction Multiple Data

Answer

Synchronized Input Memory Distribution

Answer

Systematic Integration of Modular Designs

Question 4

What does cache coherence ensure in a multiprocessor system?

Accepted Answer

All processors see a consistent and up-to-date view of shared memory

Answer

All caches have equal total capacity

Answer

Cache contents are periodically backed up to disk

Answer

Each processor's cache is encrypted independently

Question 5

What is the primary purpose of a Translation Lookaside Buffer (TLB)?

Accepted Answer

To cache recent virtual-to-physical address translations for faster memory access

Answer

To translate assembly mnemonics into machine code

Answer

To buffer data transfers between the CPU and main memory

Answer

To translate between different instruction set architectures

Question 6

What is out-of-order execution in modern processors?

Accepted Answer

Executing instructions in a different sequence than written when dependencies allow, to improve efficiency

Answer

Alternating execution between multiple programs

Answer

Skipping redundant instructions at runtime

Answer

Reordering cache lines to reduce memory latency

Question 7

What is the key architectural difference between Harvard and von Neumann architectures?

Accepted Answer

Harvard uses separate memories and buses for instructions and data; von Neumann uses one unified memory

Answer

Harvard uses transistors while von Neumann uses vacuum tubes

Answer

Harvard supports only RISC instructions while von Neumann supports CISC

Answer

Harvard uses parallel cores while von Neumann is strictly single-core